Hi! I am Naman Gupta, and I completed my MS in Electrical Engineering from University of Southern California, Los Angeles, USA in December 2015.
Previously, I have worked as a Sr. Design Engineer with Freescale Semiconductor Inc., Noida, India in the physical design domain for over 3 years between 2011 and 2014. My primary responsibilities included timing closure and constraints development. I've had the opportunity to intern for Apple Inc in Cupertino, CA working on Synthesis and PnR of a CPU block.
While at Intel Corporation in Hillsboro, Oregon I was working on the various aspects of Physical Design ranging from Synthesis to PnR.
Currently, I am working at Samsung Austin R&D Center in the GPU Implementation team responsible for EM/IR analysis along with timing convergence of a GPU sub-block.
Here's my personal webpage summarizing my work and research experience: https://sites.google.com/site/webnamangupta/
Previously, I have worked as a Sr. Design Engineer with Freescale Semiconductor Inc., Noida, India in the physical design domain for over 3 years between 2011 and 2014. My primary responsibilities included timing closure and constraints development. I've had the opportunity to intern for Apple Inc in Cupertino, CA working on Synthesis and PnR of a CPU block.
While at Intel Corporation in Hillsboro, Oregon I was working on the various aspects of Physical Design ranging from Synthesis to PnR.
Currently, I am working at Samsung Austin R&D Center in the GPU Implementation team responsible for EM/IR analysis along with timing convergence of a GPU sub-block.
Here's my personal webpage summarizing my work and research experience: https://sites.google.com/site/webnamangupta/
Here's my LinkedIn page: https://www.linkedin.com/in/namangupta89
Thanks!
Hi
ReplyDeleteI have a question. Why i have to define generated clocks instead of create_clock
I understand for create_generated clock the source is still the master clock.
1) under what conditions i will create generated clock
2) I have a mux with 2 inputs one input is clock with 1GHZ and the other input is
another clock runs at 3 GHZ.
Both the clocks cannot be active at the same time as it depends on the select signal
as the paths outside the mux are common to both the clocks, how do i do clock tree synthesis
a) how do i do CTS
b) If i meet timing for 3GHZ clock will i have to check timing for 1 GHZ.
how does primetime checks timing on these two clocks.
Please reply.
Thanks
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